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<title>Sample Waveforms for ROMifetch.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file ROMifetch.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design ROMifetch.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFFFFFF0, FFFFFFF1, FFFFFFF2, FFFFFFF3, ...). The design ROMifetch.vhd has one read port. The read port has 1024 words of 32 bits each. The output of the read port is unregistered. </P>
<CENTER><img src=ROMifetch_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. </P>
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